TSMC looks set to hit Intel where it hurts, announcing its A16 node with 'Super Power Rail' backside
Published: January 01, 0001
While Intel has been busy as [[link]] part of its accelerated roadmap towards chip making dominance, TSMC appears to have been beavering away in the background to undercut it.
It's just , which thanks to its backside power delivery implementation looks set to not only offer significantly improved performance compared to its upcoming NP2 process, but also improve energy efficiency, too. Intel has its own competing backside power delivery tech, PowerVia. While Intel says it will begin producing chips on 18A next year, it doesn't expect to start producing large volumes of chips on the .
The A16 process will make use of gate-all-around (GAAFET) nanosheet transistors alongside a backside power rail method called "Super Power Rail", which should not only improve power delivery but also increase transistor density (via ). Not only that, but TSMC has also indicated that it won't be using ASML's High NA EUV photolithography machines, which strikes as a bit of a "yah boo sucks to be you" given that very recently.
: The top chips from Intel and AMD.
: The right boards.
: Your perfect pixel-pusher awaits.
: Get into the game ahead of the rest.
It's a difficult game, the chip manufacturing business, and this new node announcement is unlikely to raise Intel's spirits in regards to its future plans.
Now then, we've all had a drink. Let's just agree that we all want some faster, more efficient silicon with better power efficiency, and that there's plenty of room for everyone [[link]] in the harmonious world of tech. No? Well then, the battle for dominance continues, I guess, and while TSMC continues to have a much stronger hand, we'll be [[link]] waiting with baited breath to see who swings next.
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